The fabrication of integrated circuits (IC) implements various patterning processes in the semiconductor wafer to define regions to be etched. Defects may be induced during patterning and/or subsequent etching. Such defects may be identified in an after-etching-inspection (AEI) stage. For example, a region to be etched can be missed or only partially etched. These patterning defects can reduce manufacturing yield and/or raise quality and reliability issues.
In current practice, a defect limit is established, and a wafer having patterning defects in excess of this limit may be scrapped while a wafer having fewer defects may proceed through fabrication. It is important to set the limit at the right amount to balance the loss of scrapping an entire wafer vs. the extra expense of continuing to fabricate a wafer that will have a relatively high number of die with defects.